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LPG SYSTEMS, M. Munck P.A. Ingénieur R&D dit : "La récupération de schéma, layout et library depuis nos précédents outils et très efficace. C'est un réel gain de temps pour la réutilisation d'anciens designs."
 


convertisseur informationCR5000 to Expedition PCB

Avaliable / Release :

PCB

Library


CR5000 to Expedition PCB:

There is one configuration file + three ‘Synchronisation’ files from Library conversion/synchronisation.


Smart layer association from configuration file: electrical layers, silkscreen, assembly and placement outline layers, mask and past layers, …

‘Synchronisation’ files to remove virtual pin or pin to be used as fiducial or mounting hole, to change cell without pin as drawing cell if needed, to remove or rename padstack. All that to reduce/remove problem during the synchronisation with a schematic project.

Trace obstructs and Via obstruct taken into account.

Traces/shape with arc data taken into account (cell and layout).

Illegal characters taken into account.

Padstack converted (viastack, padstack, mounting hole, fiducial depending of use in PCB and configuration files)

Size of text, width of line/wire taken into account.

Net name converted, same length net affected.

Clearance and NetClass converted, Rules Area Converted too.

Net Class converted.

Plane shape converted from Auto-generated copper, Auto-generated copper void can be put as ‘plane obstruct’, graphical information or deleted. (option)

Template of Copper area converted as drawn to allow verification.

PDB with simple association for the top cell and alternates cells

Blind/buried Via converted.

For each Pin and Via, check and affect specific pad on each layer (for NC_pad info) if necessary

Log files for padstack, cell, PDB and Layout Conversion.

Files with information from rules, NC_pad, Component group, net group, …


CR5000 to Expedition PCB Library:

There is one configuration file + two ‘Synchronisation’ files to help with Library conversion/synchronisation.


Smart layer association from configuration file: electrical layers, silkscreen, assembly and placement outline layers, mask and past layers, …

‘Synchronisation’ files to remove virtual pin or pin to be used as fiducial or mounting hole, to specify type of padstack. All that to reduce/remove problem during the synchronisation with a symbol+PDB library. (ex: not used at first pass, file created during PDB synchronisation, used in second pass)

Polyline/shape with arc data taken into account.

Padstack converted (viastack, padstack, mounting hole, fiducial depending on configuration files)

Pad affectation by layer, NC_pad information put in log file.

Some pad shapes conversions are done when possible (circle as round pad, drawn rectangle as rectangle pad, …), void in shape put as obstruct and in log for review.

Size of text, width of line/wire taken into account.

Reference and Part text added if not present on Package Cell.

Log files for padstack and cell Conversion, with some information files.

 
 

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